1. Field of the Invention
The present invention relates to an array substrate for a transflective liquid crystal display device and a fabrication method thereof, and more particularly, to a pad region of an array substrate for a transflective liquid crystal display device and a fabrication method thereof.
2. Discussion of the Related Art
As the information-oriented age is advancing, display devices for disposing and displaying information are actively being developed. More particularly, a flat panel display device, e.g., a liquid crystal display device, having a small thickness, lightness weight and a low power consumption, has been actively studied. The liquid crystal display device displays images by controlling a transmittance of light. In other words, a liquid crystal is interposed between two substrates facing each other, and then liquid crystal molecules move by an electric field generated from applying a voltage to electrodes, thereby the transmittance of light changes.
However, the liquid crystal display device needs a separate light source, because it does not emit a light itself. Accordingly, a backlight is disposed on the rear surface of a liquid crystal panel, and images are displayed by a light emitted from the backlight and incident to the liquid crystal panel. Above-mentioned liquid crystal display device is referred to as a transmission type liquid crystal display device. The transmission type liquid crystal display device may display bright images in a dark outside environment due to using a separate light source such as a backlight, but may have a large power consumption according to the backlight.
To solve this problem, a reflection type liquid crystal display device has been suggested. The reflection type liquid crystal display device controls a transmittance of light according to an arrangement of a liquid crystal by reflecting an outside natural light or artificial light. Although the reflection type liquid crystal display device may have lower power consumption than the transmission type liquid crystal display device, it may have low brightness when the outside light is insufficient or weak.
Accordingly, to solve these problems, a transflective liquid crystal display device complementing respective problems of the transmission type liquid crystal display device and reflection type liquid crystal display device has been suggested. The transflective liquid crystal display device may select a transmission mode using a backlight light and a reflection mode using an outside light.
FIG. 1 is a plan view illustrating an array substrate for a transflective liquid crystal display device according to a related art. As shown in FIG. 1, a pixel region P is defined by crossing a gate line 12 and a data line 14 on a transparent substrate 10, and a thin film transistor T is disposed at the crossing of the gate and data lines 12 and 14. A gate pad 40 is formed in one end of the gate line 12, and a gate pad contact hole 42 exposing a part of the gate pad 40 is formed. A pixel electrode 26 connected to the thin film transistor T through a drain contact hole 24 is formed.
The pixel region P has a reflection area RA and a transmission area TA. The reflection area RA is formed in the rest region excluding a middle region of the pixel region P, and has a reflection plate 19 formed on the pixel electrode 26. The transmission area TA is formed in the middle region of the pixel region P and does not have the reflection plate 19. An embossing pattern 30 with a convex circle shape is formed in the reflection area RA in order to prevent a specular reflection.
The thin film transistor T in the reflection area RA includes a gate electrode 16 obtaining a scan signal from the gate line 12, a source electrode 18 obtaining an image signal from the data line 14, a drain electrode 20 being apart from the source electrode 18, and an active layer 22 between the gate electrode 16 and the source and drain electrodes 18 and 20.
FIGS. 2A to 2H are cross-sectional views cutting along line II-II′ of FIG. 1 and illustrating a process of forming of an array substrate for a transflective liquid crystal display device according to the related art. FIGS. 3A to 3H are cross-sectional views cutting along line III-III′ of FIG. 1 and illustrating a process of forming of an array substrate for a transflective liquid crystal display device according to the related art. It will be explained a thin film transistor region and a gate pad region, respectively, with a four mask process.
As shown in FIG. 2A and FIG. 3A, a first metal layer 11 is formed on a transparent substrate 10. Then, as a first mask process, a photoresist 13 (it will be referred to as ‘PR layer’) of a positive type where a part receiving a light is exposed and developed is spread on the first metal layer 11, and a mask 50 having a transmission zone A and a barrier zone B is disposed on the substrate 10 having the PR layer 13. Then, the first metal layer 11 exposed by an exposing process and a developing process is etched, and then the remaining PR layer 13 is eliminated by an ashing process. As a result, the gate electrode 16 is formed in the reflection area RA of the substrate 10 as shown in FIG. 2B, and the gate pad 40 is formed in the transmission area TA of the substrate 10 as shown in FIG. 3B.
Next, as shown in FIG. 2C, a gate insulator 15, an intrinsic amorphous silicon layer 22A, an impurity-doped amorphous layer 22B, and a second metal layer 21 are formed on the entire surface of the substrate 10 having the gate electrode 16, in turn. As shown in FIG. 3C, a gate insulator 15, an intrinsic amorphous silicon layer 22A, an impurity-doped amorphous layer 22B, and a second metal layer 21 are formed on the entire surface of the substrate 10 having the gate pad 40, in turn.
Next, as shown in FIG. 2D, by a second mask process, source and drain electrodes 18 and 20 and an active layer 22 are formed. The active layer 22 refers to the exposed portion of the intrinsic amorphous silicon layer 22A. Though not shown in FIG. 2D, the second mask process will be briefly explained. A PR layer is spread on the second metal layer 21, and then a mask having a transmission-zone, a barrier-zone and a semitransparent-zone is disposed on the substrate 10 having the PR layer. The semitransparent-zone of the mask corresponds to the gate electrode 16, and the PR layer corresponding to the semitransparent-zone is exposed with only one portion. As the mask, a half-tone mask or a diffraction mask may be used. After etching the portions of the exposed second metal layer 21, the intrinsic amorphous silicon layer 22A, and the impurity-doped amorphous layer 22B, a portion corresponding to the gate electrode 16 is etched partially, thereby forming the source and drain electrodes 18 and 20 and an active layer 22. In the pad region, as the above-mentioned second mask process, the gate insulator 15 only remains as shown in FIG. 3D by using a mask having a transmission zone.
Next, as shown in FIG. 2E, a passivation layer 17 is formed by spreading one of transparent organic insulating materials such as benzocyclobutene (BCB) and acryl group resin on the source and drain electrodes 18 and 20 and the exposed gate insulator 15 as shown in FIG. 2E, and on the entire surface of the gate insulator 15 as shown in FIG. 3E.
Next, a third mask using a half-tone mask or a diffraction mask is used. As shown in FIG. 2E, a mask 60 having a transmission-zone A, a barrier-zone B and semitransparent-zone C is disposed on the substrate 10 having the passivation layer 17. The barrier-zone B and the semitransparent-zone C are alternatingly disposed for the reflection area RA in order to form the embossing pattern 30. The transmission-zone A is disposed corresponding to the drain electrode 20 in order to form a drain contact hole 24 (shown in FIG. 2F). As shown in FIG. 3E, a mask 60 having a transmission-zone A and a barrier-zone B is disposed on the substrate 10 having the passivation layer 17. The passivation layer 17 is a positive type where a part receiving a light is exposed and developed.
Next, after an exposing process, a developing process and a heat treatment are processed, an embossing-patterned passivation layer 17 and a drain contact hole 24 exposing the active layer 22 are formed as shown in FIG. 2F, and a patterned passivation layer 17 exposing a portion of the gate insulator 15 corresponding to the gate pad 40 is formed as shown in FIG. 3F.
Next, as shown in FIG. 2G, a transparent conductive material 26 and a reflection layer 19 are formed on the embossing-patterned passivation layer 17 and the gate insulator 15 exposed in the transmission area TA, in turn. The transparent conductive material 26 may be either indium-tin-oxide (ITO) or an indium-zinc-oxide (IZO). The indium-tin-oxide (ITO) 26 and the reflection layer 19 are disposed according to the shape of the embossing-patterned passivation layer 17. As shown in FIG. 3G, after a gate pad contact hole 42 exposing a portion of the gate pad 40 is formed by etching a portion of the gate insulator 15 exposed between the patterned passivation layer 17, an indium-tin-oxide (ITO) 26 and a reflection layer 19 are disposed on the patterned passivation layer 17 and exposed gate pad 40, in turn.
Next, a fourth mask using a half-tone mask or a diffraction mask is used. As shown in FIG. 2H, a PR layer 25 of a positive type is spread on the reflection layer 19, and then a half-tone mask 70 having a barrier-zone B corresponding to the reflection area RA and a semitransparent-zone C corresponding to the transmission area TA is disposed on the substrate 10 having the PR layer 25. As a result, the PR layer 25 having a height (thickness) that is ½ of the height of the PR layer 25 in the reflection area RA, is formed in the transmission area TA. The PR layer 25 in the TA of FIG. 2H is referred to as a half PR.
In the pad region of FIG. 3H, the PR layer 25 is spread on the reflection layer 19, and should be formed to have the same height as the PR layer 25 formed in the transmission area TA of FIG. 2H. However, as shown in FIG. 3H, because a step created by the patterned passivation layer 17 is high, a PR layer 25 corresponding to the transmission area TA of FIG. 3H is not formed as the same as the PR layer 25 corresponding to the transmission area TA of FIG. 2H. In other words, because a step in the pad region is high, formation of the half PR is difficult. As a result, during the ashing process that will be performed next, the indium-tin-oxide (ITO) 26 and the patterned passivation layer 17 may be damaged by the step, which in turn causes the contact between the gate pad 40 and the indium-tin-oxide (ITO) 26 to be weak or incomplete, which is a problem. Accordingly, the method of forming a transflective liquid crystal display device using the four mask process according to the related art may be ineffective, complex and expensive.